Central processing units (CPU's) which execute macroinstructions by using a series of microinstructions in a form of pipelined manner are known in the art. Pipelining microinstruction execution generally allows a faster instruction execution throughout since while one later phase or rank of a first instruction is being executed an earlier rank of a second instruction may begin to be executed.
Prior art pipelined control stores are usually sourced by an entry point table which decodes the macroinstruction to generate a pointer to the first microinstruction. That pointer is placed in a holding register from which it is used to access the control store. Subsequent microinstructions are addressed by either incrementing the value held in the holding register at each clock cycle or by using a field in the microcode of the first microinstruction to address the next and succeeding microinstructions.
The process by which a macroinstruction is used to fetch a microinstruction is usually a three clock cycle event in a two rank microcode scheme. A first clock cycle places the entry point table value in the holding register, a second clock cycle places the rank one microcode field in a register, and a third clock cycle places the rank two microcode field in a register. The registered values are then used to execute the microcode functions to actually execute the instruction. Any portion of microcode that is implemented following successive clock cycles, such as rank three or higher, is similarly executed.
Because of the nature of pipelined systems, multiple clock cycles for the execution of a single line of microcode is required. This fact of instruction execution is one of the factors which determines instruction throughput in data processing systems. Since throughput and speed are important considerations in data processing systems any improvement in the instruction execution portion of a data processing system will result in increased system performance.
Accordingly, there exists a need for a control store which is able to execute macroinstructions in fewer than the number of clock cycles which it currently takes to execute them.
It is therefore an object of the present invention to provide a control store which enables the execution of the first line of microcode of a macroinstruction in a pipelined CPU in fewer clock cycles than is possible in currently known systems.
It is a further object of the invention to provide a control store having an additional entry portion for providing the first line of microcode a clock cycle earlier than can be provided using current systems.
These and other objects of the present invention will be more clearly understood from an examination of the specification, drawings and accompanying claims.